FIG. 3 shows a prior art example of a semiconductor integrated circuit device, and FIG. 4 shows a cross-section taken along line A to A of FIG. 3. Reference numeral 1 designates a GaAs semiconductor substrate (hereinafter referred to as "substrate"). Source wirings or electrodes 2a to 2e are disposed on the substrate 1 separated from each other at equal intervals to contact the source regions of the transistors formed in substrate 1. Via-holes 3a to 3e penetrate through the substrate 1 at positions corresponding to the central portions of the source wirings 2a to 2e. The source wirings 2a to 2e are electrically connected to a grounded region 31 which is disposed at the rear surface of the substrate 1. Thus, the source wirings 2a to 2e are commonly grounded. A drain wiring or electrode 4a for contacting a drain region of the transistors is disposed at approximately centrally between the source wirings 2a and 2b on the substrate 1. Similarly, drain wiring 4b is disposed between the source wirings 2b and 2c, a drain wiring 4c is disposed between the source wirings 2c and 2d, a drain wiring 4d is disposed between the source wirings 2d and 2e. These drain wirings 4a to 4d are commonly connected after their paths extend a predetermined length in the downward direction in FIG. 3. The drain wirings 4a to 4d extend for a predetermined length because certain electrical characteristics, such as the frequency characteristics of the device, are determined by this length in a broad-band amplifier. Furthermore, a gate wiring 51 for contacting a gate region is disposed on a region of the substrate 1 which is between the source wiring 2a and the drain wiring 4a. A transistor Q1 includes the source wiring 2a, drain wiring 4a, and gate wiring 51. Similarly as above, a gate wiring 52 is provided on a region of the substrate 1 which is between by the source wiring 2b and the drain wiring 4a, and a transistor Q2 includes the source wiring 2b, drain wiring 4a, and gate wiring 52. Also, a transistor Q3 includes the source wiring 2c, drain wiring 4b, and gate wiring 53. A transistor Q4 includes the source wiring 2e, drain wiring 4b, and gate wiring 54. A transistor Q5 includes the source wiring 2c, drain wiring 4c, and gate wiring 55. A transistor Q6 includes the source wiring 2d, drain wiring 4c, and gate wiring 56. A transistor Q7 includes the source wiring 2d, drain wiring 4d and gate wiring 47. A transistor Q8 includes the source wiring 2e, drain wiring 4d, and gate wiring 58. Thus, a broad-band amplifier section 6 includes these source wirings 2a to 2d, via-holes 3a to 3e, drain wirings 4a to 4d, gate wirings 51 to 58, and transistors Q1 to Q8.
Besides, in producing via-holes 3a to 3e, the spacing between adjacent via-holes should be maintained in excess of a predetermined value. This spacing is necessary because it is technically difficult to produce the penetrating holes as via-holes 3a to 3e in substrate 1 close lower than a predetermined value because the penetrating holes are produced by etching, and because mutual interferences between via-holes 3a to 3e must be considered.
Generally, in producing a broad-band amplifier on a semiconductor chip, the configuration of the semiconductor chip is determined by the layout of the broad-band amplifier section 6, that is, by the configuration of the broad-band amplifier section 6.
Accordingly, in the prior art semiconductor integrated circuit device in which the via-holes 3a to 3e are laid out on a straight line on the semiconductor substrate 1, the broad-band amplifier section 6 becomes relatively long and narrow. As a result, the semiconductor chip becomes also relatively long and narrow, thereby reducing the number of the semiconductor chips which can be produced from a wafer (hereinafter referred to as "theoretical chip number") when compared with a case where a square chip of the same area is employed. Furthermore, there may be unused space on the substrate 1 because the lengths of the drain wirings 4a to 4d should be established at values larger than a predetermined value based on the electrical characteristics of the device, which unfavourably results in an increase in the area of the broad-band amplifier section 6, and in turn, an increase in the chip area and reduction in the theoretical chip number.